COLLEGE OF ENGINEERING
Electrical Engineering
EE223 Analog Integrated Circuits
Section 01
FALL 2020
Course and Contact Information
- Instructor: Sang-Soo Lee
- Office Location: ENGR 259
- Phone: (408) 924-3950
- Email: sang-soo.lee@sjsu.edu
- Office Hours: MW 4:00 PM - 4:45 PM or Other time by appointment
- Class Days/Time: MW 7:30 PM - 8:45 PM
- Classroom: Online Zoom Meeting
- Prerequisites: Graduate Standing or instructor consent
- GE/SJSU Studies Category:
Course Description
This course studies nanoscale metal-oxide semiconductor field effect transistor (MOSFET) modeling and circuit design techniques for analog integrated circuit applications. Course topics include short channel issues, layout techniques to improve design performance, noise modeling and transformation, high-swing current mirrors, bandgap and reference circuits, gain and bandwidth characteristics of single-stage and two-stage amplifiers. A variety of operational amplifier architectures including fully-differential structures with their slew rate, settling time, phase margin, stability will be discussed in detail. Finally, the application of the fully-differential operational amplifiers in switched-capacitor circuits is discussed.Course Format
OnlineService Learning or Credit Bearing Internships
Faculty Webpage and MySJSU Messaging
https://www.sjsu.edu/people/sang-soo.lee/Program Information
Course Goals
GE Learning Outcomes
Course Learning Outcomes (CLO)
Students will acquire the ability to: characterize and model MOS transistors, bias and operate transistors in amplifiers with different characteristics, understand high performance layout with minimum parasitic, utilize Cadence Spectre circuit simulation tools to characterize various analog circuits, determine the trade-off among linearity, bandwidth, gain and power dissipation of amplifiers, design stable multi-stage amplifiers, apply frequency compensation techniques for amplifiers, design temperature and supply independent bandgap reference and switched-capacitor circuits.
Upon successful completion of this course, students will be able to:
- Design advanced biasing circuits, operational amplifiers, and switched-capacitor circuits.
- Understand the concept of noise, distortion, stability, phase margin, voltage swing, slew-rate and gain-bandwidth product of amplifiers.
- Use modern engineering CAD tools for computations, simulations, analysis, and design of analog and mixed-signal circuits.
- Verify the theory with hands-on Cadence Spectre circuit simulations.
Required Texts, Readings, and Technology
Textbook
No textbook required. Instructor will provide lecture notes, reading and resource materials relevant to the topics discussed in the lecture.
Other Readings
Lecture notes, slides, and technical papers will be posted in Canvas. The following reference books are recommended as supplementary readings.
- Design of Analog CMOS Integrated Circuits, 1st Edition, by Behzad Razavi McGraw-Hill, 2001
- CMOS Circuit Design, Layout, and Simulation, 3rd Edition, by R. Jacob Baker, IEEE Press, Wiley, 2010
- Analog Integrated Circuit Design, 2nd Edition, by Tony Chan Carusone, David A. Johns and K. Martin, Wiley, 2011
- Analysis and Design of Analog Integrated Circuits, 5th Edition, by Gray, Hurst, Lewis and Meyer, Wiley, 2009
Other Technology Requirements / Equipment / Material
To be successful in this course, make sure your computers or devices have:
- Reliable Internet access
- VPN (Links to an external site.) & remote access to connect to SJSU Cadence Lab computer
- Access to Canvas. Ensure your web browser and browser settings are Canvas compatible
Library Liasion
Course Requirements and Assignments
Homework assignments and the final design project are mainly based on Cadence Spectre simulations and are closely related to the topics discussed in the class. Information on how to setup and run the Cadence simulation tools will be provided and students are required to master this CAD tool by themselves. The final design project will be a group project. Each group (maximum 3 students) must write a formal project report using a word processor (i.e. Microsoft Office) and submit the original write-up including all data, images, and graphs to Canvas before deadline to be eligible to receive a credit. Students may be required to present their works like standard design reviews as conducted in industry. Non-restricted MOSFET transistor models will be provided for assignments and the project. More details on the design project will be provided as the lectures progress.
“Success in this course is based on the expectation that students will spend, for each unit of credit, a minimum of 45 hours over the length of the course (normally three hours per unit per week) for instruction, preparation/studying, or course related activities, including Cadence Spectre simulations. Other course structures will have equivalent workload expectations as described in the syllabus.”
Final Examination or Evaluation
The date of the exams is shown on the course schedule section of the course syllabus. Exams will be online open book. There will be no make-up exam and those absent will receive no credit. Students must write their answers clearly in an organized fashion and submit the answer sheets to Canvas. Further instructions will be provided 2 weeks before the exams.
Grading Information
| Homework | 20% |
| Midterm exam | 25% |
| Design project | 25% |
| Final exam | 30% |
Determination of Grades
| 90% and above | A |
| 89% - 85% | A minus |
| 84% - 82% | B plus |
| 81% - 79% | B |
| 78% - 75% | B minus |
| 74% - 72% | C plus |
| 71% - 69% | C |
| 68% - 65% | C minus |
| 64% - 62% | D plus |
| 61% - 59% | D |
| 58% - 55% | D minus |
| below 55% | F |
Classroom Protocol
Students will turn their cell phones off or put them on vibrate mode while in class. They will not answer their phones in the class. During the online class, students will mute themselves unless they need to speak for questions and answers.
Classroom Recording Policy
Students are not allowed to record (audio or video) in this class except in accordance with ADA accommodations. Any recordings made in connection with a disability accommodation are for the student’s personal academic use only and may not be distributed in any manner to any other individual. Students are not allowed to post class materials in any online site. Instructor may record certain lectures and post them in Canvas for those who cannot attend the online lecture for any reason. Students are not allowed to post class materials including videos in any other online site.
University Policies
Per University Policy S16-9, university-wide policy information relevant to all courses, such as academic integrity and accommodations will be available on Office of Graduate and Undergraduate Programs’ Syllabus Information web page.
Additional Information
This course is offered only in FALL semester.
EE Department Honor Code
The Electrical Engineering Department will enforce the following Honor Code that must be read and accepted by all students.
“I have read the Honor Code and agree with its provisions. My continued enrollment in this course constitutes full acceptance of this code. I will NOT:
- Take an exam in place of someone else, or have someone take an exam in my place
- Give information or receive information from another person during an exam
- Use more reference material during an exam than is allowed by the instructor
- Obtain a copy of an exam prior to the time it is given
- Alter an exam after it has been graded and then return it to the instructor for re-grading
- Leave the exam room without returning the exam to the instructor.”
Measures Dealing with Occurrences of Cheating
- Department policy mandates that the student or students involved in cheating will receive an “F” on that evaluation instrument (paper, exam, project, homework, etc.) and will be reported to the Department and the University.
- A student’s second offense in any course will result in a Department recommendation of suspension from the University.
Course Schedule
| Week | Date | Topics, Readings, Assignments, Deadlines |
|---|---|---|
| 1 | 8/19 | No class - cancelled due to air quality concern |
| 2 | 8/24 | Course Introduction |
| 2 | 8/26 | Circuit Basics |
| 3 | 8/31 | CMOS Fabrication |
| 3 | 9/2 | CMOS scaling and design flow |
| 4 | 9/7 | No class - Labor Day |
| 4 | 9/9 | MOS I-V characteristics |
| 5 | 9/14 | MOS small-signal model |
| 5 | 9/16 | Common source amplifiers |
| 6 | 9/21 | Common source with source degeneration |
| 6 | 9/23 | Common gate amplifiers |
| 7 | 9/28 | Source follower |
| 7 | 9/30 | Cascode amplifiers |
| 8 | 10/5 | Folded-cascode and differential pair |
| 8 | 10/7 | Current mirrors |
| 9 | 10/12 | Beta multiplier |
| 9 | 10/14 | MOSFET matching |
| 10 | 10/19 | Midterm exam, online open book |
| 10 | 10/21 | Midterm solution |
| 11 | 10/26 | Bandgap reference |
| 11 | 10/28 | Project description |
| 12 | 11/2 | Gain boosting technique |
| 12 | 11/4 | Frequency response |
| 13 | 11/9 | OTA |
| 13 | 11/11 | No class - Veteran's Day |
| 14 | 11/16 | Feedback and stability |
| 14 | 11/18 | Two-stage OPAMP |
| 15 | 11/23 | Class AB amplifiers |
| 15 | 11/25 | No class - Thanksgiving Holiday |
| 16 | 11/30 | Noise in amplifiers |
| 16 | 12/2 | Switched-capacitor circuits |
| 17 | 12/7 | Fully-differential amplifier circuits |
| 17 | 12/9 | Final exam (7:45 PM - 10:00 PM), online open book |
