COLLEGE OF ENGINEERING 

Electrical Engineering 

EE230 RFIC II 

Section 01 

FALL  2020

Course and Contact Information

  • Instructor: Sang-Soo Lee
  • Office Location: ENGR 259
  • Phone: (408) 924-3950
  • Email: sang-soo.lee@sjsu.edu
  • Office Hours: MW 5:00 PM - 5:45 PM
  • Class Days/Time: MW 6:00 PM - 7:15 PM  
  • Classroom: Online Zoom Meeting
  • Prerequisites: Graduate Standing or instructor consent
  • GE/SJSU Studies Category:  

Course Description

This course studies modern RF transceiver architectures and key RF transceiver building blocks including CMOS low noise amplifiers (LNA), Mixers, Oscillators, phase-locked loops (PLL), Frequency Synthesizers and Power Amplifier (PA) along with advanced layout techniques and analytic skills to improve the noise, linearity, stability, efficiency and bandwidth of RF communication circuits for WiFi, Bluetooth, and 5G cellular applications. Students will utilize Cadence Spectre RF circuit simulation tools to characterize various RF circuits, determine the trade-off among noise, distortion, linearity, bandwidth, gain, and power dissipation of the RF circuits. 

Course Format

Online

Service Learning or Credit Bearing Internships

 

Faculty Webpage and MySJSU Messaging

https://www.sjsu.edu/people/sang-soo.lee/

Program Information

 

Course Goals

 

GE Learning Outcomes

 

Course Learning Outcomes (CLO)

Students will acquire the ability to: characterize and model RF components, understand the operation of popular circuit architectures used in LNA, Mixer, VCO, PLL, Frequency Synthesizer, and PA.

Upon successful completion of this course, students will acquire:

  • The ability to understand the RF components and their impact on the performance of the RF circuits
  • The ability to understand methods and simulation tools to characterize complex RF integrated circuits
  • The ability to understand key requirements and calculate design parameters for LNA, Mixer, Oscillator, VCO, PLL, Frequency Synthesizer, and Power Amplifier circuits.
  • The ability to understand and model the loop characteristics and stability of PLL in Verilog-A and to design charge-pump PLL and Frequency Synthesizer circuits in transistor level implementation
  • The ability to verify the theory with hands-on Spectre RF circuit simulations
  • The ability to perform team work and analyze the operation of wireless transmitters and receivers

Required Texts, Readings, and Technology

Textbook

No textbook required. Instructor will provide lecture notes, reading and resource materials relevant to the topics discussed in the lecture.

Other Readings

 

The following references are recommended as supplementary readings.

  1. B. Razavi, RF Microelectronics, 2nd Edition, Upper Saddle River, New Jersey, Prentice Hall, 2012
  2. T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge, U.K., Cambridge University Press, 2004.
  3. Selected publications from journal of solid-state circuits (JSSC), transactions on microwave theory and techniques (MTT), international solid-state circuits conference (ISSCC) and custom integrated circuits conference (CICC). Papers can be downloaded from IEEE Xplore website. 

Other Technology Requirements / Equipment / Material

To be successful in this course, make sure your computers or devices have: 

  • Reliable Internet access
  • VPN (Links to an external site.) & remote access to connect to SJSU Cadence Lab computer
  • Access to Canvas. Ensure your web browser and browser settings are Canvas compatible
 

Library Liasion

 

Course Requirements and Assignments

Assignments and projects are mainly based on Cadence SpectreRF simulations and are closely related to topics discussed in this course. Information on how to setup and run the Cadence simulation tools will be provided and students are required to master this CAD tool by themselves. The final design project will be a group project.  Each group (maximum 2 students) must write a formal project report using a word processor (i.e. Microsoft Office) and submit the original write-up including all data, images, and graphs to Canvas before deadline to be eligible to receive a credit. Students may be required to present their works like standard design reviews as conducted in industry. Non-restricted MOSFET transistor models will be provided for assignments and the project. More details on the design project will be provided as the lectures progress.

 “Success in this course is based on the expectation that students will spend, for each unit of credit, a minimum of 45 hours over the length of the course (normally three hours per unit per week) for instruction, preparation/studying, or course related activities, including but not limited to internships, labs, and clinical practice. Other course structures will have equivalent workload expectations as described in the syllabus.”

Final Examination or Evaluation

The date of the exams is shown on the course schedule section of the course syllabus. Exams will be online open book. There will be no make-up exam and those absent will receive no credit. Students must write their answers clearly in an organized fashion and submit the answer sheets to Canvas. Further instructions will be provided 2 weeks before the exams.

Grading Information

Homework 15%
Midterm exam 25%
Design project 25%
Final exam 35%

Determination of Grades

90% and above A
89% - 85%  A minus
84% - 82%  B plus
81% - 79%  B
78% - 75%  B minus
74% - 72%  C plus
71% - 69%  C
68% - 65%  C minus
64% - 62%  D plus
61% - 59%  D
58% - 55%  D minus
below 55%  F

Classroom Protocol

Students will turn their cell phones off or put them on vibrate mode while in class. They will not answer their phones in the class. During the online class, students will mute themselves unless they need to speak for questions and answers.

Classroom Recording Policy

Students are not allowed to record (audio or video) in this class except in accordance with ADA accommodations. Any recordings made in connection with a disability accommodation are for the student’s personal academic use only and may not be distributed in any manner to any other individual. Students are not allowed to post class materials in any online site. Instructor may record certain lectures and post them in Canvas for those who cannot attend the online lecture for any reason. Students are not allowed to post class materials including videos in any other online site.

University Policies

Per University Policy S16-9, university-wide policy information relevant to all courses, such as academic integrity and accommodations will be available on Office of Graduate and Undergraduate Programs’ Syllabus Information web page.

Additional Information

This course is offered only in FALL semester.

EE Department Honor Code

The Electrical Engineering Department will enforce the following Honor Code that must be read and accepted by all students.

“I have read the Honor Code and agree with its provisions. My continued enrollment in this course constitutes full acceptance of this code. I will NOT:

  • Take an exam in place of someone else, or have someone take an exam in my place
  • Give information or receive information from another person during an exam
  • Use more reference material during an exam than is allowed by the instructor
  • Obtain a copy of an exam prior to the time it is given
  • Alter an exam after it has been graded and then return it to the instructor for re-grading
  • Leave the exam room without returning the exam to the instructor.”

Measures Dealing with Occurrences of Cheating

  • Department policy mandates that the student or students involved in cheating will receive an “F” on that evaluation instrument (paper, exam, project, homework, etc.) and will be reported to the Department and the University.
  • A student’s second offense in any course will result in a Department recommendation of suspension from the University.

Course Schedule

Week Date Topics, Readings, Assignments, Deadlines
1 8/19 No class - cancelled due to air quality concern
2 8/24 Course Introduction
2 8/26 Noise and linearity
3 8/31 Resonance circuit and Impedance transformation
3 9/2 S-parameters and Smith Chart
4 9/7 No class - Labor Day
4 9/9 RF receiver architecture & Low noise amplifier 1
5 9/14 Low noise amplifier 2
5 9/16 Low noise amplifier 3
6 9/21 Low noise amplifier 4
6 9/23 Mixer 1
7 9/28 Mixer 2
7 9/30 Mixer 3
8 10/5 Oscillator 1
8 10/7 Oscillator 2
9 10/12 Midterm exam, Online open book
9 10/14 VCO 1
10 10/19 VCO 2
10 10/21 PLL 1
11 10/26 PLL 2
11 10/28 PLL 3
12 11/2 Frequency Synthesizer
12 11/4 Power Amplifier 1
13 11/9 Power Amplifier 2
13 11/11 No class - Veteran's Day
14 11/16 RF transmitter architecture
14 11/18 RF systems & transceiver architecture 
15 11/23 5G and WiGig RF front-end circuits
15 11/25 No class - Thanksgiving Holiday
16 11/30 Proejct presentation - Group A
16 12/2 Project presentation - Group B
17 12/7 Course review
17 12/12 Final exam (5:00 PM - 7:00 PM), online open book