Publications & Presentations

Choo, Chang Y

Publications & Patents (Selected)

“Performance Evaluation of FPGA-Based Bit-Scaled CNN Architecture,” Intel HPC Developer Conference, Denver, Colorado, Nov. 11-12, 2017 (with B.J. Kim).

“SGDR: A Simple GPS-Based Disrupt-Tolerant Routing for Vehicular Networks," 8th Intern. Conf. ICT Convergence, Jeju Island, Oct. 18-20, 2017 (with H.Y. Jung).

“FPGA-Based Hardware Accelerator for Feature Extraction in Automatic Speech Recognition,” Int. J. lnfo. Commun. Converg. Eng. 13(3): 145-151, Sep. 2015 (with Y.U. Chang and I.Y. Moon).

“Novel Write request handling for Static Wear Leveling in Flash Memory (SSD) Controller,” Int. J. lnfo. Commun. Converg. Eng. 12(3): 181-185, Sep. 2014 (with P. Gajipara and I.Y. Moon).

“FPGA-Based Design of Black Scholes Financial Model for High Performance Trading,” Int. J. lnfo. Commun. Converg. Eng. 11(3): 190-198, Sep. 2013 (with L. Malhotra and A. Munjal).

“FPGA Design of a Real-Time Edge Enhancing Smoothing Filter,” IS&T/SPIE Electronic Imaging, Burlingame, California, Feb. 3-7, 2013 (with N. Pandya).

“An FPGA-Based Embedded Wideband Audio Codec System,” 19th international Conference on Field Programmable Logic and Applications, Prague, Czech Republic, Aug. 31-Sep. 2, 2009.  

“Design of High-Performance Adaptive FIR Filters Using FPGA,” DesignCon, Santa Clara, California, Feb. 4-7, 2008.

“FPGA-Based Hardware Accelerator for Rank and Median Filters for Image processing,” 4th Conference on New Exploratory Technologies, Seoul, Korea, Oct. 25-27, 2007 (with P. Verma).

“FPGA-Based Embedded Acoustic Echo Canceller System,” 4th Conference on New       Exploratory Technologies, Seoul, Korea, Oct. 25-27, 2007 (with W. Zhang).

“Economic Effects of Indirect Access Regime in the Mobile Telecommunication Market,” 35th Research Conference on Communication, Information and Internet Policy, George MasonUniversitySchool of Law, Arlington, Virginia, Sep. 28-30, 2007 (with B.W. Kim).

 “An Embedded Adaptive Filtering System on FPGA,” GSPx Conference, Santa Clara, CA, Oct. 30-Nov. 2, 2006 (with P. Padmanabhan, et al.).

“Implementation of Texas Instruments TMS32010 DSP Processor on Altera FPGA,” GSPx Conference, Santa Clara, CA, September 27-30, 2004 (with J. Chung, et al.).

“Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation,” IP Based SOC Design Workshop, Grenoble, France, October 30-31, 2002.

“A Memory Reduction Scheme for Multi-Channel Echo Canceller Implementation,” Proc. IEEE International Conf. Acoustics, Sound, and Signal Processing, Salt Lake City, Utah, pp.3301-3304, May 7-11, 2001 (with H. Elabd).

“Designing High-Performance Echo Canceller for VOIP,” DSP Engineering Mag., vol.2, no.1, pp. 12-26, 2000.

“Constrained Variable-Bit-Rate Control Algorithm for MPEG-2 Encoder,” Proc. SPIE, vol. 3974, pp.133-143, Image and Video Communications and Processing 2000, B. Vasudev; T.R. Hsing; A.G. Tescher; R.L. Stevenson; Eds. (with D. Zhang).

“Optimization of 2D median filtering algorithm for VLIW architecture,” Proc. SPIE, vol.3970, pp. 70-79, Media Processors 2000, S. Panchanathan; V.M. Bove; S.I. Sudharsanan; Eds. (with M. Tang).

“Design and Implementation of Digital FIR Filters Using Altera FIR Compiler,” DSP and Multimedia Magazine, 1999.

“Video Applications for Distributed Arithmetic,” tutorial workshop paper, ICSPAT-99,  Orlando, Florida, November 1999.

“Syntax-Based Arithmetic Video Coding for Very Low Bitrate Visual Telephony,” Proc. IEEE Intern. Conf. Image Processing, Washington, DC, pp.II410-II413, Oct. 22-25, 1995 (with X. Ran).

“Evaluation of Design Parameters for a Cache Vector Quantization System,”  Proc. First IEEE Conference on Image Processing, Austin, Texas, pp. 129-133, Nov. 13-16, 1994 (with N. M. Nasrabadi).

H.26P/TMN2-NSC: National Semiconductor Implementation of ITU H.26P Draft        Recommendation on Video Coding for Narrow Telecommunication Channels at < 64        kbits/s, Confidential Technical Report, Corporate Technology Group, National        Semiconductor, Santa Clara, California, September, 1994 (with X. Ran, et al.).

“Dynamic Finite-State Vector Quantization of Digital Images,” IEEE Transactions on  Communications, vol.42, no.5, pp.2145-2154, May 1994 (with N. M. Nasrabadi and Y.      Feng).

“Performance Analysis of a Vector Quantizer with Cache Memory,” Proc. 27th Annual  Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp.    956-960, Nov. 1-3, 1993 (with B. A. Cicchetto and N. M. Nasrabadi).

“Interframe Hierarchical Address-Vector Quantization,” IEEE Journal on Selected Areas in Communications, vol. 10, no. 5, pp. 960-967, June 1992 (with N. M. Nasrabadi and J.U. Roy).

“Hopfield Network for Stereo Vision Correspondence,” IEEE Transactions on Neural    Networks, vol. 3, no. 1, pp. 5-13, January 1992 (with N. M. Nasrabadi).

“A TMS320C25-Based Implementation of Motion-Compensated Interframe Image Coding System,” Proc. First Texas Instruments TMS320 Educators Conference, Houston, Texas, pp. 215-228, July 31 –August 2, 1991 (with N. M. Nasrabadi).

“A Self-Organizing Adaptive Vector Quantization Technique,” Journal of Visual      Communication and Image Representation, vol. 2, no. 2, pp. 129-137, June 1991 (with N.M. Nasrabadi and Y. Feng).

“A Multiprocessor System for Interframe Hierarchical Address-Vector Quantization,” Proc. 1991 IEEE International Symposium on Circuits and Systems, Singapore, pp. 61-64, June 11-14, 1991 (with F. J. Desjarlais and N. M. Nasrabadi).

“Hierarchical Block Truncation Coding of Digital HDTV Images,” IEEE Transactions on Consumer Electronics, vol.36, no.3, pp.254-261, August 1990 (with N.M. Nasrabadi, et al.).

“Design and Analysis of Two-Channel High Definition Television Systems,” IEEE Trans. on Broadcasting, vol. 36, no. 2, pp.175-183, June 1990 (with N.M. Nasrabadi).



U.S. Patent No. 9,025,763 (2015) “Apparatus and Method for cancelling wideband acoustic echo,” (with I.K. Hwang).

U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006) “Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices,” (with A. Hazanchuk).

U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003) “Motion vector based frame insertion process for increasing the frame rate of moving images”

U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999) “Hashing-based vector quantization,” (with X. Ran).

U.S. Patent No. 5,587,710 (1997) “Syntax based arithmetic coder and decoder,” (with X. Ran, et al.).