Wong, Hiu Yung
Silicon Valley AMDT Endowed Chair in Electrical Engineering
- Ph.D. EECS, University of California, Berkeley (2006)
- M.Phil. Computer Science and Engineering, Chinese University of Hong Kong (2001)
- B. Eng. Computer Engineering, Chinese University of Hong Kong (1999)
Hiu Yung Wong is an Assistant Professor and Silicon Valley AMDT Endowed Chair in Electrical Engineering, San Jose State University. He received his Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 2006. From 2006 to 2009, he worked as a Technology Integration Engineer in Spansion. From 2009 to 2018, he was a TCAD Senior Staff Application Engineer in Synopsys, during which he received Synopsys Excellence Award in 2010. In 2021, he received the NSF CAREER award and the Newnan Brothers Award for Faculty Excellence.
His research interests include the applications of machine learning in simulation and manufacturing, cryogenic electronics, quantum computing, reliability simulations, wide bandgap devices (such as GaN, SiC, Ga2O3, and diamond) simulations, novel semiconductor devices design and Design Technology Co-Optimization (DTCO). His work has produced 80 papers and 10 issued patents.
- Silicon Valley AMDT Endowed Chair in Electrical Engineering, 2022
- NSF CAREER Award, 2021
- Newnan Brothers Award for Faculty Excellence, 2021. (demonstrate excellence in some combination of teaching, service to students, and/or research.)
- Synopsys Excellence Award (1 out of every ~500 employees), 2010
- Sir Edward Youde Memorial Fellowships for Overseas Studies, 2001
Associate Editor, IEEE Access
Guest Editor, JVST-B, speical issue on "Reliability and Stress-related Phenomena in Nano and Microelectronics"
- Technical Program Committee (TPC) for International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2020-)
- Co-Chair, 16th International Conference on Reliability and Stress-related Phenomena in Nano and Microelectronics (IRSP 2019)
- IEEE EDS-SCV/SF Secretary (2018 -2019) Treasurer (2019-)
- IEEE EDS-SCV/SF executive committee board (2018 - )
- Senior Member of Institute of Electrical and Electronics Engineers (IEEE)
- Workshop Moderator: “Circuit Reliability: Advanced nodes concerns and CAD tools flows” 2018 IEEE International Reliability Physics Symposium (IRPS)
- Reviewer: IEEE Electron Device Letter (EDL) and others
- Judge: The Synopsys Championship (the Santa Clara County science fair for students in grades 6-12), Sciencepalooza! (for students in grades 9-12 in East San José)